Synchronizing latches are used in a wide variety of applications. For example, with integrated circuit devices such as system-on-a-chip (SOC) devices and multi-core processors, signals can travel between different clock domains. When entering a different domain, they typically need to be synchronized with the different domain clock. For example, a signal may originate from flops in one clock domain (or from an asynchronous domain) and have a destination in a different clock domain. This is often associated with functions running at different frequencies but may also, for example, happen with source-synchronous data arriving at a destination running at the same frequency. In any case, synchronization is usually achieved by clocking key signals with the receiving clock through 1 or more flip flops. In such cases, the setup/hold time of the flip-flops may often be violated. At times, the flip-flop may have difficulty resolving to a '1 or a '0. This is commonly referred to as “metastability.” If the metastability lasts too long, the signals may be corrupted and cause a design to fail. some solutions involve the Use of multiple, serial flip-flops to reduce the chance of failure, but unfortunately, this approach adds latency. Other approaches involve increasing transistor sizes in the flip-flop circuits to increase their responsiveness and resolve a value. Unfortunately, however, this costs power and at reduced voltages, metastability problems can dramatically increase, especially with respect to other logic performance criterion. Especially in reduced power designs, this can make synchronization challenging. Accordingly, new synchronization solutions are desired.